Responsibilities :
    Participate in the development of high-performance ASICs from specification to tape-out, including RTL, Synthesis, physical design, and timing closure
    Maintain and enhance existing designs using Verilog/SystemVerilog
    Participate in the Implementation of new designs using Verilog / SystemVerilog
    Triage and troubleshoot failures down to the root cause
    Actively work with the verification team to deliver ASICs with high quality
    Actively work with the physical design team to resolve implementation and timing issues
    Develop tests and debug ASICs in the emulation
    Perform diagnostics and tests for ASICs in the lab

Education and Experience Required :
    Bachelors or Masters degree in Electrical Engineering.
    7+ years of ASIC design experience.

    Experience with Synthesis, Timing/Power Analysis.

Preferred Qualifications :

• Experience in designing multi-million gate blocks with multiple clock domains.
• Strong understanding of ARM CHI, AXI, AHB, APB standards and experience with PCIE, LPDDR, Ethernet standards is a definite plus
• Hands on experience in Design Verification and/or physical design is a plus.
• Familiarity with high performance and low power design techniques.

Knowledge and Skills :
      Excellent Verilog, System Verilog programming and debugging skills.
      Scripting experience (Python, Perl, TCL, shell programming).
      Proficient in synthesis constraints.
      Ability to write and debug test.
      Ability to debug system-wide issues.
      Good written and verbal communication skills.
      Collaborative and team-focused with the drive to learn and grow.