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As Hardware Design Engineer your main responsibilities will include
- Solid understanding of both FE and BE ASIC flows
- Close interaction with RTL and Designer Verification teams
- Writing Verilog code, run simulation, debug waveforms
- Understanding of gate level netlist synthesis flow
- Power, performance and area optimization of design
- Development of new utilities and scripts
Who You'll Work With
In addition to working alongside talented colleagues, candidates will have many opportunities to learn through coaching and stretch assignment opportunities. They will be guided by feedback and support to accelerate the learning and maximize their knowledge.
Who You Are
Essential requirements:
* BS/MS in Electrical Engineering or Computer Science
* 10+ year minimum of hands-on experience in ASIC design
* Understanding of ASIC design methodology and flow all the way from netlist to GDSII.
* Writing block architecture document, implement design in Verilog/Systems Verilog
* Run simulation, debug waveforms.
* Works with Design Verification engineer
* Optimize design for timing, power and area
* Knowledge of scripting languages Tcl, Python
* Excellent English verbal and written communication skills.
* Understands the big picture and attention to detail during execution
* Self-motivated, able to work independently or as a team player
When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S. locations, not including equity or benefits. For non-sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses. Hiring ranges for sales positions include base and incentive compensation target. Individual pay is determined by the candidate's hiring location and additional factors, including but not limited to skillset, experience, and relevant education, certifications, or training. Applicants may not be eligible for the full salary range based on their U.S. hiring location. The recruiter can share more details about compensation for the role in your location during the hiring process.
Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components. For quota-based incentive pay, Cisco pays at the standard rate of 1% of incentive target for each 1% revenue attainment against the quota up to 100%. Once performance exceeds 100% quota attainment, incentive rates may increase up to five times the standard rate with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.
