14 days old

Low Power Methodology Engineer

San Diego, CA
QCT is actively seeking candidates for the low-power design and methodology team. This team is responsible for defining and implementing low-power techniques, power models, and processes for ensuring power budgets are understood and tracked as key design parameter across QCTs global development of wireless communications chips. In this role, the engineer is responsible for working with numerous SOC technology teams to deliver power efficient designs. This will involve understanding the power metrics of key SOC use cases and participation in optimizing hardware, software, and firmware for reaching these low power metrics. The ideal candidate will be able to guide multi-function groups in establishing power budgets and assist teams through the development cycle in realizing such power targets. The candidate should be familiar with power analysis tools for both assessing power reduction opportunities as well as projecting power estimations. The candidate should be familiar with the ASIC design flow from specification through physical design and be familiar with modeling power consumption of IP within a complex SOC. Experience with correlating pre-silicon power estimates with post-silicon measurements is desired. Experience with Database use and management for tracking, referencing, and mining large volume of data is highly desired. Experience with Power Intent (e.g. UPF) is a plus.
All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.
Minimum Qualifications
  • Bachelor's degree in Science, Engineering, or related field.
  • 5+ years ASIC design, verification, or related work experience.
    Preferred Qualifications 5-10 years of experience in low power digital ASIC design, power analysis and modeling
  • Understanding of electrical engineering concepts, circuit analysis and logic design skills
  • Familiarity with advanced low power techniques and high speed clocking desired
  • Familiarity with power integrity and power distribution
  • Programming languages: Verilog, Python, Perl, C++, C-shell, UNIX
  • Tool Familiarity: PowerArtist, Calypto PowerPro, Synopsys PrimeTime, PTPX, QlikView, ThoughtSpot, Modelsim, VCS, Debussy, Spyglass, and MS-Office
  • Database Familiarity: MongoDB, SQL

    Education Requirements Required: Bachelor's, Computer Engineering and/or Electrical Engineering
    Preferred: Master's, Computer Engineering and/or Electrical Engineering

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    San Diego, CA

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    San Diego, CA

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